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74ALVC163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
November 2001 Revised November 2001
74ALVC163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
General Description
The ALVC163245 is a dual supply, 16-bit translating transceiver that is designed for 2 way asynchronous communication between busses at different supply voltages by providing true signal translation. The supply rails consist of VCCA, which is a higher potential rail operating at 2.3V to 3.6V and VCCB, which is the lower potential rail operating at 1.65V to 2.7V. (VCCB must be less than or equal to VCCA for proper device operation). This dual supply design allows for translation from 1.8V to 2.5V busses to busses at a higher potential, up to 3.3V. The Transmit/Receive (T/R) input determines the direction of data flow. Transmit (active-HIGH) enables data from A Ports to B Ports; Receive (active-LOW) enables data from B Ports to A Ports. The Output Enable (OE) input, when HIGH, disables both A and B Ports by placing them in a High-Z condition. The A Port interfaces with the higher voltage bus (2.7V to 3.3V); The B Port interfaces with the lower voltage bus (1.8V to 2.5V). Also the ALVC163245 is designed so that the control pins (T/Rn, OEn) are supplied by VCCB. The 74ALVC163245 is suitable for mixed voltage applications such as notebook computers using a 1.8V CPU and 3.3V peripheral components. It is fabricated with an Advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s Bidirectional interface between busses ranging from 1.65V to 3.6V s Supports Live Insertion and Withdrawal (Note 1) s Uses patented Quiet Series noise/EMI reduction circuitry s Functionally compatible with 74 series 16245 s Latchup conforms to JEDEC JED78 s ESD performance: Human Body Model >2000V Machine model >200V s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)
Note 1: To ensure the high impedance state during power up or power down, OEn should be tied to VCCB through a pull up resistor. The minimum value of the resistor is determined by the current sourcing capability of the driver.
Ordering Code:
Order Number 74ALVC163245GX (Note 2) 74ALVC163245T (Note 3) Package Number BGA54A (Preliminary) MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [Tape and Reel] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only. Note 3: Device also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
(c) 2001 Fairchild Semiconductor Corporation
ds500695
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74ALVC163245
Logic Diagram
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Names OEn T/Rn A0-A15 B0-B15 NC Description Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs No Connect
FBGA Pin Assignments
1 A B C D E F G H J B0 B2 B4 B6 B8 B10 B12 B14 B15 2 NC B1 B3 B5 B7 B9 B11 B13 NC 3 T/R1 NC VCCB GND GND GND VCCB NC T/R2 4 OE1 NC VCCA GND GND GND VCCA NC OE2 5 NC A1 A3 A5 A7 A9 A11 A13 NC 6 A0 A2 A4 A6 A8 A10 A12 A14 A15
Truth Tables
Inputs Pin Assignment for FBGA OE1 L L H Inputs OE2 L L H T/R2 L H X Outputs Bus B8-B15 Data to Bus A8-A15 Bus A8-A15 Data to Bus B8-B15 HIGH-Z State on A8-A15, B8-B15 T/R1 L H X Outputs Bus B0-B7 Data to Bus A0-A7 Bus A0-A7 Data to Bus B0-B7 HIGH Z State on A0-A7, B0-B7
(Top Thru View)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance
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74ALVC163245
74ALVC163245 Translator Power Up Sequence Recommendations
To guard against power up problems, some simple guidelines need to be adhered to. The 74ALVC163245 is designed so that the control pins (T/Rn, OEn) are supplied by VCCB. Therefore the first recommendation is to begin by powering up the control side of the device, VCCB. The OEn control pins should be ramped with or ahead of VCCB, this will guard against bus contentions and oscillations as all A Port and B Port outputs will be disabled. To ensure the high impedance state during power up or power down, OEn should be tied to VCCB through a pull up resistor. The minimum value of the resistor is determined by the current sourcing capability of the driver. Second, the T/Rn control pins should be placed at logic LOW (0V) level, this will ensure that the B-side bus pins are configured as inputs to help guard against bus contention and oscillations. B-side Data Inputs should be driven to a valid logic level (0V or VCCB), this will prevent excessive current draw and oscillations. VCCA can then be powered up after VCCB, however VCCA must be greater than or equal to VCCB to ensure proper device operation. Upon completion of these steps the device can then be configured for the users desired operation. Following these steps will help to prevent possible damage to the translator device as well as other system components.
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ALVC163245
Absolute Maximum Ratings(Note 4)
Supply Voltage VCCA VCCB DC Input Voltage (VI) DC Output Voltage (VI/O) (Note 5) An Bn DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or Ground Current Supply Pin (ICC or Ground) Storage Temperature (TSTG)
Recommended Operating Conditions (Note 6)
Power Supply (Note 7) VCCA VCCB Input Voltage (VI) @ OE, T/R Input/Output Voltage (VI/O) An Bn Free Air Operating Temperature (TA Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 0V to VCCA 0V to VCCB 2.3V to 3.6V 1.65V to 2.7V 0V to VCCB
-0.5V to +4.6V -0.5V to VCCA -0.5V to +4.6V -0.5V to VCCA + 0.5V -0.5V to VCCB + 0.5V -50 mA -50 mA 50 mA 100 mA -65C to +150C
-40C to +85C
10 ns/V
Note 4: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused inputs or I/O pins must be held HIGH or LOW. They may not float. Note 7: Operation requires: VCCB VCCA
DC Electrical Characteristics
Symbol VIHA Parameter HIGH Level Input Voltage An Conditions VCCB (V) 1.65 - 1.95 1.65 - 2.7 VIHB VILA LOW Level Input Voltage Bn, T/R, OE An 1.65 - 1.95 2.3 - 2.7 1.65 - 1.95 1.65 - 2.7 VILB VOHA HIGH Level Output Voltage Bn, T/R, OE IOH = -100 A IOH = -12 mA IOH = -24 mA VOHB HIGH Level Output Voltage IOH = -100 A IOH = -4 mA IOH = -12 mA VOLA Low Level Output Voltage IOL = 100 A IOL = 12 mA IOL = 24 mA VOLB Low Level Output Voltage IOL = 100 A IOL = 4 mA IOL = 12 mA II IOZ Input Leakage Current @ OE, T/R 3-STATE Output Leakage 0V VI 3.6V 0V VO 3.6V OE = VCCB VI = VIH or VIL IOFF ICCA/ICCB ICC Power Off Leakage Current Quiescent Supply Current, per supply, VCCA / VCCB Increase in ICC per Input, Bn, T/R, OE Increase in ICC per Input, An 0 (VI, VO) 3.6V An = V CCA or GND Bn, OE, & T/R = VCCB or GND VI = VCCB - 0.6V VI = VCCA - 0.6V 0 1.65 - 2.7 1.65 - 2.2 1.65 - 2.2 0 2.3 - 3.6 2.3 - 3.6 2.3 - 3.6 10 40 750 750 A A A A 1.65 - 2.7 2.3 - 3.6 10 A 1.65 - 1.95 2.3 - 2.7 1.65 - 2.7 1.65 1.65 - 2.3 1.65 - 2.7 1.65 - 1.95 2.3 - 2.7 1.65 - 2.7 1.65 1.65 - 2.3 1.65 - 2.7 1.65 - 1.95 2.3 -2.7 1.65 - 2.7 VCCA (V) 2.3 - 2.7 3.0 - 3.6 2.3 - 3.6 3.0 - 3.6 2.3 - 2.7 3.0 - 3.6 2.3 - 3.6 3.0 - 3.6 2.3 - 3.6 2.3 - 2.7 3.0 - 3.6 2.3 - 3.6 2.3 - 3.0 3.0 2.3 - 3.6 2.3 - 2.7 3.0 - 3.6 2.3 - 3.6 2.3 - 3.0 3.0 2.3 - 3.6 VCCA-0.2 1.7 2 VCCB-0.2 1.2 1.7 0.2 0.7 0.55 0.2 0.45 0.7 5.0 A V V V V Min 1.7 2.0 V 0.65 x VCCB 1.6 0.7 0.8 V 0.35 x VCCB 0.7 Max Units
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74ALVC163245
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 Symbol Parameter VCCA = 3.3 0.3 VCCB = 2.5 0.2 VCCA = 3.3 0.3 VCCB = 1.8 0.15 VCCA = 2.7 VCCB = 1.8 0.15 VCCA = 2.5 0.2 VCCB = 1.8 0.15 tPHL, tPLH Propagation Delay B to A VCCA = 3.3 0.3 VCCB = 2.5 0.2 VCCA = 3.3 0.3 VCCB = 1.8 0.15 VCCA = 2.7 VCCB = 1.8 0.15 VCCA = 2.5 0.2 VCCB = 1.8 0.15 tPZL, tPZH Output Enable Time OE to B VCCA = 3.3 0.3 VCCB = 2.5 0.2 VCCA = 3.3 0.3 VCCB = 1.8 0.15 VCCA = 2.7 VCCB = 1.8 0.15 VCCA = 2.5 0.2 VCCB = 1.8 0.15 tPZL, tPZH Output Enable Time OE to A VCCA = 3.3 0.3 VCCB = 2.5 0.2 VCCA = 3.3 0.3 VCCB = 1.8 0.15 VCCA = 2.7 VCCB = 1.8 0.15 VCCA = 2.5 0.2 VCCB = 1.8 0.15 tPLZ, tPHZ Output Disable Time OE to B VCCA = 3.3 0.3 VCCB = 2.5 0.2 VCCA = 3.3 0.3 VCCB = 1.8 0.15 VCCA = 2.7 VCCB = 1.8 0.15 VCCA = 2.5 0.2 VCCB = 1.8 0.15 tPLZ, tPHZ Output Disable Time OE to A VCCA = 3.3 0.3 VCCB = 2.5 0.2 VCCA = 3.3 0.3 VCCB = 1.8 0.15 VCCA = 2.7 VCCB = 1.8 0.18 VCCA = 2.5 0.2 VCCB = 1.8 0.18 1.1 1.1 1.3 5.3 6.1 5.7 0.8 5.2 0.6 5.6 ns 1.3 1.3 1.3 4.9 5.0 5.1 0.8 4.6 0.8 4.5 ns 1.1 1.1 1.3 4.5 5.6 5.8 0.8 5.3 0.6 5.1 ns 1.3 2.0 2.0 5.1 8.7 8.8 1.5 8.3 1.5 8.2 ns 1.1 1.1 1.3 4.5 5.6 6.0 0.8 5.5 0.6 5.1 ns CL = 50 pF Min tPHL, tPLH Propagation Delay A to B 1.3 2.0 2.0 Max 4.9 6.7 6.3 1.5 5.8 1.5 6.2 ns CL = 30 pF Min Max Units
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74ALVC163245
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VI = 0V or VCC VI = 0V or VCC Outputs Enabled f = 10 MHz, CL = 50 pF TA = +25C VCC 3.3 3.3 3.3 2.5 Typical 5 6 20 20 Units pF pF pF
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74ALVC163245
AC Loading and Waveforms
TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND
FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50) Symbol Vmi Vmo VX VY VL VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2 1.8V 0.15V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2
FIGURE 2. Waveform for Inverting and Non-inverting Functions tr = tf 2.0 ns, 10% to 90%
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic tr = tf 2.0 ns, 10% to 90%
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic tr = tf 2.0 ns, 10% to 90%
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74ALVC163245
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A (Preliminary)
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74ALVC163245 Low Voltage 16-Bit Dual Supply Translating Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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